Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits. Integrated circuits include field-effect transistors (FETs) such as metal oxide semiconductor (MOS) transistors.
One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs. However, isolating devices in FETs with sub 65 nm transistor nodes has presented challenges. For example, etching a shallow trench isolation (STI) region trench and filling the STI trench with insulator material becomes more difficult.
One attempt to overcome such challenges involved using tetraethoxysilane (TEOS) as an isolation material. However, use of TEOS may lead to an undesirable humidity absorption concern. In more advanced technology FETs, an oxide is deposited in the STI trench using a high aspect ratio process (HARP) or a Spin-On Glass (SOG) process for device isolation. However, these approaches may require a specific trench profile in order to be successful. For example, an aspect ratio of the STI trench, which is a ratio of the depth to width, may have to be relatively high (e.g., at or above 5). In addition, a slope of the trench may be restricted (e.g., at or below 87 degrees).
In addition to the above, when the STI trench is filled with an insulating material using the HARP process, tensile stress is induced in a channel of the FET and the FET is really only suitable as an NMOS device. On the other hand, when the STI trench is filled using a high density plasma (HDP) process, compressive stress is induced in the channel of the FET and the FET is only really suitable as a PMOS device.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.